Stefano Tommesani

Floating-Point Intrinsics

Arithmetic Operation Intrinsics

a0 [op] b0

a1

a0 [op] b0

a1 [op] b1

a0 [op] b0

a1

a0 [op] b0

a1 [op] b1

a0 [op] b0

a1

a0 [op] b0

a1 [op] b1

a0 [op] b0

a1

a0 [op] b0

a1 [op] b1

a0 [op] b0

a1

a0 [op] b0

a1 [op] b1

a0 [op] b0

a1

a0 [op] b0

a1 [op] b1

a0 [op] b0

a1

a0 [op] b0

a1 [op] b1

Logical Operations

__m128d _mm_andnot_pd (__m128d a, __m128d b);
ANDNPD

Computes the bitwise AND of the 128-bit value in b and the bitwise NOT of the 128-bit value in a.

r0 := (~a0) & b0 
r1 := (~a1) & b1 
__m128d _mm_and_pd (__m128d a, __m128d b);
ANDPD 

Computes the bitwise AND of the two double-precision, floating-point values of a and b.

r0 := a0 & b0
r1 := a1 & b1
__m128d _mm_or_pd (__m128d a, __m128d b);
ORPD

Computes the bitwise OR of the two double-precision, floating-point values of a and b.

r0 := a0 | b0
r1 := a1 | b1
__m128d _mm_xor_pd (__m128d a, __m128d b);
XORPD

Computes the bitwise XOR of the two double-precision, floating-point values of a and b .

r0 := a0 ^ b0
r1 := a1 ^ b1

Comparison Intrinsics

Conversion Operations

Miscellaneous Operations

__m128d _mm_unpackhi_pd (__m128d a, __m128d b);
UNPCKHPD

Interleaves the upper double-precision, floating-point values of a and b.

r0 := a1
r1 := b1
__m128d _mm_unpacklo_pd (__m128d a, __m128d b);
UNPCKLPD

Interleaves the lower double-precision, floating-point values of a and b.

r0 := a0
1 := b0
int _mm_movemask_pd (__m128d a);
MOVMSKPD

Creates a two-bit mask from the sign bits of the two double-precision, floating-point values of a.

r := sign(a1) << 1 | sign(a0)
__m128d _mm_shuffle_pd (__m128d a, __m128d b, int i);
SHUFPD

Selects two specific double-precision, floating-point values from a and b, based on the mask i. The mask must be an immediate. See Macro Function for Shuffle Using Streaming SIMD Extensions 2 Instructions section for a description of the shuffle semantics.

Integer Intrinsics

Integer Arithmetic Operations

Logical Operations Intrinsics

an explanation of the syntax used in code samples in this topic, see Floating-Point Intrinsics Using Streaming SIMD Extensions.

__m128i _mm_and_si128 (__m128i a, __m128i b);
PAND

Computes the bitwise AND of the 128-bit value in a and the 128-bit value in b.

r := a & b
__m128i _mm_andnot_si128 (__m128i a, __m128i b);
PANDN

Computes the bitwise AND of the 128-bit value in b and the bitwise NOT of the 128-bit value in a.

r := (~a) & b
__m128i _mm_or_si128 (__m128i a, __m128i b);
POR

Computes the bitwise OR of the 128-bit value in a and the 128-bit value in b.

r := a | b
__m128i _mm_xor_si128 ( __m128i a, __m128i b);
PXOR

Computes the bitwise XOR of the 128-bit value in a and the 128-bit value in b.

r := a ^ b

Shift Operation Intrinsics

Conversion Intrinsics

__m128i _mm_cvtsi32_si128 (int a);
MOVD

Moves 32-bit integer a to the least significant 32 bits of an __m128 object one extending the upper bits.

r0 := a
r1 := 0x0 ; r2 := 0x0 ; r3 := 0x0
int _mm_cvtsi128_si32 (__m128i a);
MOVD

Moves the least significant 32 bits of a to a 32-bit integer.

r := a0

Comparison Intrinsics

Miscellaneous Operations Intrinsics

Cache Support Intrinsics

void _mm_stream_pd (double *p, __m128d a);
MOVLPD

Stores the data in a to the address p without polluting caches. The address p must be 16-byte aligned. If the cache line containing address p is already in the cache, the cache will be updated.

p[0] := a0
p[1] := a1 

Integer Load Operation

__m128i _mm_load_si128 (__m128i *p);
MOVDQA

Loads 128-bit value. Address p must be 16-byte aligned.

r := *p
__m128i _mm_loadu_si128 (__m128i *p);
MOVDQU

Loads 128-bit value. Address p does not need be 16-byte aligned.

r := *p
__m128i _mm_loadl_epi64(__m128i const*p);
MOVQ

Load the lower 64 bits of the value pointed to by p into the lower 64 bits of the result, zeroing the upper 64 bits of the result.

r0:= *p[63:0]
r1:=0x0

Integer Set Operation Intrinsics

Integer Store Operation Intrinsics

void _mm_store_si128 (__m128i *p, __m128i a);
MOVDQA

Stores 128-bit value. Address p must be 16-byte aligned.

*p := a
void _mm_storeu_si128 (__m128i *p, __m128i a);
MOVDQU

Stores 128-bit value. Address p does not need to be 16-byte aligned.

*p := a
void _mm_maskmoveu_si128(__m128i d, __m128i n, char *p);
MASKMOVDQU

Conditionally store byte elements of d to address p. The high bit of each byte in the selector n determines whether the corresponding byte in d will be stored. Address p does not need to be 16-byte aligned.

if (n0[7]) p[0] := d0
if (n1[7]) p[1] := d1
...
if (n15[7]) p[15] := d15
void _mm_store1_epi64(__m128i *p, __m128i a);
MOVQ

Stores the lower 64 bits of the value pointed to by p.

*p[63:0]:=a0

Cache Support

void _mm_stream_si128(__m128i *p, __m128i a)

Stores the data in a to the address p without polluting the caches. If the cache line containing address p is already in the cache, the cache will be updated. Address p must be 16-byte aligned.

*p := a
void _mm_stream_si32(int *p, int a)

Stores the data in a to the address p without polluting the caches. If the cache line containing address p is already in the cache, the cache will be updated.

*p := a
void _mm_clflush(void const*p)

Cache line containing p is flushed and invalidated from all caches in the coherency domain.

void _mm_lfence(void)

Guarantees that every load instruction that precedes, in program order, the load fence instruction is globally visible before any load instruction that follows the fence in program order.

void _mm_mfence(void)

Guarantees that every memory access that precedes, in program order, the memory fence instruction is globally visible before any memory instruction that follows the fence in program order.

void _mm_pause(void)

The execution of the next instruction is delayed an implementation specific amount of time. The instruction does not modify the architectural state.

Shuffle Function Macro

_MM_SHUFFLE2(x, y)
/* expands to the value of */
(x<<1) | y

You can view the two integers as selectors for choosing which two words from the first input operand and which two words from the second are to be put into the result word.

View of Original and Result Words with Shuffle Function Macro