Stefano Tommesani

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Results 81 - 100 of 110

Various/Photos
Copenhagen/images
Thursday, 06 January 2011 | Print | PDF |  E-mail | Report
Various/Racing
  abarth    
Monday, 03 January 2011 | Print | PDF |  E-mail | Report
Various/Photos
SanPietroburgo/images
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report
84. Budapest
Various/Photos
Budapest
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report
Programming/SIMD
Any computer, whether sequential or parallel, operates by executing instructions on data. A stream of instructions (the algorithm) tells the computer what to do at each step. A stream of data (the input to the algorithm) is affected by these...
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...
Programming/SIMD
The MMX technology is designed to accelerate multimedia and communications applications by including new instructions and data types that allow applications to achieve a new level of performance. It exploits the parallelism inherent in many...
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...
Programming/SIMD
The Intel Streaming SIMD Extensions (SSE) comprise a set of extensions to the Intel x86 architecture that is designed to greatly enhance the performance of advanced media and communication applications. In this section the SSE integer...
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...
Programming/SIMD
The MMX technology supports both saturating and wraparound modes. In wraparound mode, results that overflow or underflow are truncated and only the lower (least significant) bits of the result are returned. In saturation mode, results of an...
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...
Programming/SIMD
These instructions generate a mask of ones or zeros which can be used by logical operations to select elements within a register: a developer can implement a packed conditional move operation without a set of branch instructions.  ...
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...
Programming/SIMD
There are several cases where elements of packed data may be required to be repositioned within the packed data, or the elements of two packed data operands may need to be merged. There are cases where either input or the desired output...
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...
Programming/SIMD
When stored in memory the bytes, words, and doublewords in the packed data types are stored in consecutive addresses, with the least significant byte, word, or doubleword being stored in the lowest address and the more significant bytes, words,...
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...
92. MMX EMMS
Programming/SIMD
The EMMS instruction empties the MMX state. This instruction must be used to clear the MMX state (i.e. empty the floating-point tag word) at the end of an MMX routine before calling other routines that can execute floating-point instructions. If...
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...
Programming/SIMD
This section describes example uses of the MMX instruction set to implement basic coding structures. Conditional Select Operating on multiple data operands using a single instruction presents an interesting issue: what happens when a ...
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...
Programming/SIMD
PAND mm, mm/m64 PANDN mm, mm/m64 POR mm, mm/m64 PXOR mm, mm/m64 The PAND (Bitwise Logical And), PANDN (Bitwise Logical And Not), POR (Bitwise Logical OR), and PXOR (Bitwise Logical Exclusive OR) instructions perform bitwise...
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...
95. MMX Shift
Programming/SIMD
The logical shift left, logical shift right and arithmetic shift right instructions shift each element by a specified number of bits. The logical left and right shifts also enable a 64-bit quantity (quadword) to be shifted as one block, assisting...
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...
Programming/SIMD
The MMX instructions are supported by every x86 processor introduced in the market after the venerable Intel Pentium MMX, so it should be fairly safe to assume that the processor that your code is running on has MMX instructions. But checking ...
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...
Programming/SIMD
The Intel P6 core, introduced with the Pentium Pro processor and used in all current Intel processors, features a RISC-like microarchitecture and an out-of-order execution unit, representing a radical shift from previous designs. The P6's new...
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...
Programming/SIMD
The following table lists the Instruction Sets supported by each processor. Processor MMX Extended MMX SSE SSE2 3DNow! Intel Pentium Intel Pentium MMX ...
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...
Programming/SIMD
The following table summarizes the latencies of MMX/iSSE instructions on the Intel Pentium III and Pentium 4 processors, and on the AMD Athlon processor: Instruction Pentium III Pentium 4 AMD Athlon MOVD mm,r32 1...
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...
Programming/SIMD
The recent arrival of the Intel Pentium 4 processor has generated the usual flurry of benchmarks and comments, most of them emphasizing that current software does not fully exploit the power of this new architecture (click here for an overview...
Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...

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