Stefano Tommesani

1. SSE2 Intrinsics

Floating-Point Intrinsics Arithmetic Operation Intrinsics Intrinsic name Corresponding instruction Operation R0 value R1 value _mm_add_sd ADDSD Adds a0 [op] b0 a1 ...

Monday, 27 May 2013 | Print | PDF |  E-mail | Report | More...

2. MMX Intrinsics

General Support Intrinsics Intrinsic name Operation Signed Saturation Assembly instruction _mm_empty Empties MM state Not applicable Not applicable EMMS _mm_cvtsi32_si64 Converts from int Not applicable Not...

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3. SSE Intrinsics

Packed Arithmetic Intrinsics Intrinsic Instruction Operation R0 R1 R2 R3 _mm_add_ss ADDSS Adds a0 [op] b0 a1 a2 ...

Monday, 27 May 2013 | Print | PDF |  E-mail | Report | More...

4. Comparing SSE2 and GPGPU C++AMP

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Monday, 20 May 2013 | Print | PDF |  E-mail | Report

5. Different types of parallel loops with SSE2, SSSE3 and Visual C++ 2012

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Wednesday, 01 May 2013 | Print | PDF |  E-mail | Report

6. SSE2 64-bit FP instructions

In the introduction we have outlined the applications that require 64-bit precision, scientific simulations and CAD/CAM being notable examples. However, the transition from normal scalar code to 64-bit floating-point SSE2 code is complex and it...

Friday, 26 April 2013 | Print | PDF |  E-mail | Report | More...

7. SSE2 and MMX

I’'m quite sure that Intel would not like to see SSE2 named 128-bit MMX. In fact, MMX has a bad reputation: the Intel marketing hype pushed it as an universal solution to multimedia requirements, but at the same time the gaming industry switched...

Friday, 26 April 2013 | Print | PDF |  E-mail | Report | More...

8. 3DNow!

The latest trend in PC games is 3D graphics: during the past few years, almost all kinds of games have turned to 3D graphics, greatly increasing the demand of processors with strong floating-point performance, because the front end of a typical...

Friday, 26 April 2013 | Print | PDF |  E-mail | Report | More...

9. SSE Introduction

The Streaming SIMD Extensions enhance the Intel x86 architecture in four ways: 8 new 128-bit SIMD floating-point registers that can be directly addressed; 50 new instructions that work on packed floating-point data; 8...

Friday, 26 April 2013 | Print | PDF |  E-mail | Report | More...

10. SSE Conversion

These instructions support packed and scalar conversions between 128-bit SIMD floating-point registers and either 64-bit integer MMX registers or 32-bit integer x86 registers. CVTPI2PS converts two 32-bit signed integers in an MMX register...

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11. SSE Logical

ANDPS returns a bitwise AND between the two operands. ANDNPS returns a bitwise AND NOT between the two operands. ORPS returns a bitwise OR between the two operands. XORPS returns a bitwise XOR between the two operands. ...

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12. SSE Comparison

The basic single precision FP comparison instruction is similar to existing MMX instruction variants: it produces a redundant mask per float of all 1’s or all 0’s, depending upon the result of the comparison. This approach allows the mask to...

Friday, 26 April 2013 | Print | PDF |  E-mail | Report | More...

13. SSE Shuffle

SHUFPS is able to shuffle any of the numbers from one source operand to the lower two destination fields; the upper two destination fields are generated from a shuffle of any of the four SP FP numbers from the second source operand. By using...

Thursday, 25 April 2013 | Print | PDF |  E-mail | Report | More...

14. SSE Arithmetic

ADDPS (parallel) and ADDSS (scalar) add the pair of operands. SUBPS (parallel) and SUBSS (scalar) subtract the pair of operands. MULPS (parallel) and MULSS (scalar) multiply the pair of operands. DIVPS (parallel) and DIVSS (scalar)...

Thursday, 25 April 2013 | Print | PDF |  E-mail | Report | More...

15. SSE Data Movement

MOVAPS transfers 128 bits of packed data from memory to SIMD floating-point registers and vice versa, or between SIMD floating-point registers, while MOVUPS makes no assumption for alignment. MOVHPS transfers 64 bits of packed data from...

Thursday, 25 April 2013 | Print | PDF |  E-mail | Report | More...

16. Programming models

Any computer, whether sequential or parallel, operates by executing instructions on data. A stream of instructions (the algorithm) tells the computer what to do at each step. A stream of data (the input to the algorithm) is affected by these...

Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...

17. MMX Primer

The MMX technology is designed to accelerate multimedia and communications applications by including new instructions and data types that allow applications to achieve a new level of performance. It exploits the parallelism inherent in many...

Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...

18. SSE Primer

The Intel Streaming SIMD Extensions (SSE) comprise a set of extensions to the Intel x86 architecture that is designed to greatly enhance the performance of advanced media and communication applications. In this section the SSE integer...

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19. MMX Arithmetic

The MMX technology supports both saturating and wraparound modes. In wraparound mode, results that overflow or underflow are truncated and only the lower (least significant) bits of the result are returned. In saturation mode, results of an...

Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...

20. MMX Comparison

These instructions generate a mask of ones or zeros which can be used by logical operations to select elements within a register: a developer can implement a packed conditional move operation without a set of branch instructions.  ...

Tuesday, 30 November 1999 | Print | PDF |  E-mail | Report | More...