SSE2 Intrinsics

Floating-Point Intrinsics Arithmetic Operation Intrinsics Intrinsic name Corresponding instruction Operation R0 value R1 value _mm_add_sd ADDSD Adds a0 [op] b0 a1 _mm_add_pd ADDPD Adds a0 [op] b0 a1 [op] b1 _mm_div_sd DIVSD Divides a0 [op] b0 a1 _mm_div_pd DIVPD Divides…

SSE Intrinsics

Packed Arithmetic Intrinsics Intrinsic Instruction Operation R0 R1 R2 R3 _mm_add_ss ADDSS Adds a0 [op] b0 a1 a2 a3 _mm_add_ps ADDPS Adds a0 [op] b0 a1 [op] b1 a2 [op] b2 a3 [op] b3 _mm_sub_ss SUBSS Subtracts a0 [op] b0…

MMX Intrinsics

General Support Intrinsics Intrinsic name Operation Signed Saturation Assembly instruction _mm_empty Empties MM state Not applicable Not applicable EMMS _mm_cvtsi32_si64 Converts from int Not applicable Not applicable MOVD _mm_cvtsi64_si32 Converts from int Not applicable Not applicable MOVD _mm_packs_pi16 Packs Yes…

SSE Arithmetic

ADDPS (parallel) and ADDSS (scalar) add the pair of operands. SUBPS (parallel) and SUBSS (scalar) subtract the pair of operands. MULPS (parallel) and MULSS (scalar) multiply the pair of operands.DIVPS (parallel) and DIVSS (scalar) divides the pair of operands. SQRTPS…

SSE2 and MMX

layout-sse2

I’’m quite sure that Intel would not like to see SSE2 named 128-bit MMX. In fact, MMX has a bad reputation: the Intel marketing hype pushed it as an universal solution to multimedia requirements, but at the same time the…

MMX Shift

The logical shift left, logical shift right and arithmetic shift right instructions shift each element by a specified number of bits. The logical left and right shifts also enable a 64-bit quantity (quadword) to be shifted as one block, assisting…

MMX Logical

PAND mm, mm/m64 PANDN mm, mm/m64 POR mm, mm/m64 PXOR mm, mm/m64 The PAND (Bitwise Logical And), PANDN (Bitwise Logical And Not), POR (Bitwise Logical OR), and PXOR (Bitwise Logical Exclusive OR) instructions perform bitwise logical operations on 64-bit quantities.…