The logical shift left, logical shift right and arithmetic shift right instructions shift each element by a specified number of bits. The logical left and right shifts also enable a 64-bit quantity (quadword) to be shifted as one block, assisting in data type conversions and alignment operations.   PSLLW mm,…

PAND mm, mm/m64 PANDN mm, mm/m64 POR mm, mm/m64 PXOR mm, mm/m64 The PAND (Bitwise Logical And), PANDN (Bitwise Logical And Not), POR (Bitwise Logical OR), and PXOR (Bitwise Logical Exclusive OR) instructions perform bitwise logical operations on 64-bit quantities. The destination operand is an MMX register, while the source…

This section describes example uses of the MMX instruction set to implement basic coding structures. Conditional Select Operating on multiple data operands using a single instruction presents an interesting issue: what happens when a computation is only done if the operand value passes some conditional check? For example, in an…

MMX was Intel’s first widely used SIMD instruction set for x86 processors. It introduced packed integer operations that could process multiple small values at once inside a single 64-bit register. For its time, this was extremely useful. MMX made it possible to accelerate image processing, audio processing, video decoding, graphics…

When stored in memory the bytes, words, and doublewords in the packed data types are stored in consecutive addresses, with the least significant byte, word, or doubleword being stored in the lowest address and the more significant bytes, words, or doubleword being stored at consecutively higher addresses. The ordering of…

There are several cases where elements of packed data may be required to be repositioned within the packed data, or the elements of two packed data operands may need to be merged. There are cases where either input or the desired output representation of a data may not be ideal…

These instructions generate a mask of ones or zeros which can be used by logical operations to select elements within a register: a developer can implement a packed conditional move operation without a set of branch instructions.

The MMX technology supports both saturating and wraparound modes. In wraparound mode, results that overflow or underflow are truncated and only the lower (least significant) bits of the result are returned. In saturation mode, results of an operation that overflow or underflow are clipped (saturated) to a data-range limit for…

Intel’s Streaming SIMD Extensions, better known as SSE, are often associated with 128-bit floating-point operations on XMM registers. That is the part of SSE most developers remember today: four single-precision floating-point values packed into one register and processed with one instruction. However, the original SSE instruction set did more than…

MMX was the first widely adopted SIMD instruction set on x86 processors. It was introduced by Intel in the Pentium MMX generation and later supported by AMD and other x86-compatible processors. At the time, it was a major step forward for multimedia and communications software because it allowed one instruction…