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  • Programming
    • SIMD on x64/x86
    • Multi-thread
    • C# and .NET
    • Testing
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  • Marketing
  • SIMD on x64/x86

    MMX EMMS: Why _mm_empty() Is Required After MMX Code

    April 24, 2010

    MMX was Intel’s first widely used SIMD instruction set for x86 processors. It introduced packed integer operations that could process multiple small values at once inside a single 64-bit register. For its time, this was extremely useful. MMX made it possible to accelerate image processing, audio processing, video decoding, graphics…

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  • SIMD on x64/x86

    MMX Data Transfer: loading, storing, and moving packed integers

    April 24, 2010

    When stored in memory the bytes, words, and doublewords in the packed data types are stored in consecutive addresses, with the least significant byte, word, or doubleword being stored in the lowest address and the more significant bytes, words, or doubleword being stored at consecutively higher addresses. The ordering of…

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  • SIMD on x64/x86

    MMX Conversion Instructions: packing, unpacking, and reordering data

    April 24, 2010

    There are several cases where elements of packed data may be required to be repositioned within the packed data, or the elements of two packed data operands may need to be merged. There are cases where either input or the desired output representation of a data may not be ideal…

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  • SIMD on x64/x86

    MMX Comparison Instructions: building masks for packed integers

    April 24, 2010

    These instructions generate a mask of ones or zeros which can be used by logical operations to select elements within a register: a developer can implement a packed conditional move operation without a set of branch instructions.

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  • SIMD addition
    SIMD on x64/x86

    MMX Arithmetic Instructions: Wrapping, Saturation, and Packed Multiplication

    April 24, 2010

    The MMX technology supports both saturating and wraparound modes. In wraparound mode, results that overflow or underflow are truncated and only the lower (least significant) bits of the result are returned. In saturation mode, results of an operation that overflow or underflow are clipped (saturated) to a data-range limit for…

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  • SIMD on x64/x86

    SSE Integer Instructions: the MMX extensions introduced with SSE

    April 24, 2010

    Intel’s Streaming SIMD Extensions, better known as SSE, are often associated with 128-bit floating-point operations on XMM registers. That is the part of SSE most developers remember today: four single-precision floating-point values packed into one register and processed with one instruction. However, the original SSE instruction set did more than…

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  • SIMD on x64/x86

    MMX Primer: Packed Integer SIMD on Early x86 CPUs

    April 24, 2010

    MMX was the first widely adopted SIMD instruction set on x86 processors. It was introduced by Intel in the Pentium MMX generation and later supported by AMD and other x86-compatible processors. At the time, it was a major step forward for multimedia and communications software because it allowed one instruction…

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  • SISD
    SIMD on x64/x86

    Programming models

    April 24, 2010

    Any computer, whether sequential or parallel, operates by executing instructions on data. A stream of instructions (the algorithm) tells the computer what to do at each step. A stream of data (the input to the algorithm) is affected by these instructions. A widely used classification of parallel systems, due to…

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  • SIMD on x64/x86

    SSE State Management: MXCSR, FXSAVE, FXRSTOR, and FP control

    April 25, 2000

    SSE state management is the part of SIMD programming concerned with the processor state used by SSE floating-point instructions. Most SSE code does not need explicit state management. If you are writing ordinary code with intrinsics such as _mm_add_ps, _mm_mul_ps, _mm_loadu_ps, and _mm_storeu_ps, the compiler, operating system, and calling convention…

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  • sse04
    SIMD on x64/x86

    SSE Shuffle

    April 25, 2000

    SHUFPS is able to shuffle any of the numbers from one source operand to the lower two destination fields; the upper two destination fields are generated from a shuffle of any of the four SP FP numbers from the second source operand. By using the same register for both sources,…

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Vintage CPUs of the day

  • Intel Pentium III 800EB Intel Pentium III 800EB
  • AMD Athlon X2 7750 AMD Athlon X2 7750
  • AMD K6-2 500 MHz AMD K6-2 500 MHz
  • Intel Pentium MMX 200 MHz Intel Pentium MMX 200 MHz

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