MOVAPS transfers 128 bits of packed data from memory to SIMD floating-point registers and vice versa, or between SIMD floating-point registers, while MOVUPS makes no assumption for alignment. MOVHPS transfers 64 bits of packed data from memory to the upper two fields of a SIMD floating-point register and vice versa,…
SSE introduced 128-bit XMM registers and a new set of SIMD instructions for single-precision floating-point arithmetic. Alongside arithmetic, comparison, shuffle, and logical operations, SSE also added several important conversion instructions. These conversion instructions move data between two worlds: The original SSE conversion instructions are: They are easy to overlook, but…
The basic single precision FP comparison instruction is similar to existing MMX instruction variants: it produces a redundant mask per float of all 1?s or all 0?s, depending upon the result of the comparison. This approach allows the mask to be used with subsequent logic operations (AND, ANDN, OR, XOR)…
Data referenced by a program can have temporal (data will be used again) or spatial (data will be in adjacent locations, such as the same cache line) locality, but some multimedia data types are referenced once and not reused in the immediate future (called non-temporal data). Thus, non-temporal data should…
In the introduction we have outlined the applications that require 64-bit precision, scientific simulations and CAD/CAM being notable examples. However, the transition from normal scalar code to 64-bit floating-point SSE2 code is complex and it may require some major design changes. A more conservative approach would be moving to scalar…
SSE2, short for Streaming SIMD Extensions 2, was one of the most important instruction-set extensions in the history of x86 processors. It was introduced by Intel with the Pentium 4 processor, code-named Willamette, as the successor to the original SSE instruction set. At the time, SSE2 was presented as an…
The recent arrival of the Intel Pentium 4 processor has generated the usual flurry of benchmarks and comments, most of them emphasizing that current software does not fully exploit the power of this new architecture (click here for an overview of the SSE2 instruction set). However, until the Pentium 4…
Instruction latency is one of the most important details to understand when optimizing SIMD code. A SIMD instruction may look simple at the source-code level, but the number of cycles required before its result can be used depends heavily on the exact instruction, operand type, vector width, instruction encoding, and…
The original version of this article was written in 2000, when the practical SIMD landscape on x86 processors was still small enough to fit in a compact table. At that time, the important questions were simple: That map was useful because the market was transitioning from scalar x86 code to…
The Intel P6 core, introduced with the Pentium Pro processor and used in all current Intel processors, features a RISC-like microarchitecture and an out-of-order execution unit, representing a radical shift from previous designs. The P6’s new dynamic execution micro-architecture removes the constraint of linear instruction sequencing between the traditional fetch…